• Overview
• System Design and Validation
• Application/ IP Development and Customization
• Embedded System Design

SoftJin's Verification Approach

SoftJin's Verification approach consists of deploying an appropriate mix of techniques to meet the verification objectives. Based on the stage of the design and the verification objectives to be met, SoftJin deploys an appropriate Verification methodology. The methodology will typically consist of a combination of some of the following elements:

• Creation of a detailed Verification Plan to establish Verification metrices and report progress.
• Reusable SystemC Testbenches at various abstraction levels (Transaction Level, Cycle Accurate, RTL).
• Development and use of Verification IPs like Bus Functional Models (BFMs). Use of BFMs isolates modeling concerns in DUT and Testbench. Also, these are re-usable components that improve verification productivity across designs.
• Constraint driven random verification techniques to achieve maximum coverage. These cover corner cases which are difficult to cover using Directed Test Cases.
• Assertion based verification (both internal and external to DUT). Use of assertions at external interfaces verifies protocol of interaction of DUT with outside world. Use of assertions internal to DUT verifies and monitors critical points of design without writing Testbenches.
• Use of Automated Regression environment to support multi-CPU execution of verification tasks and automatically generate reports.
• Use of Synthesizable Test benches for faster verification with large real-life test data.
• Hardware-Software co-verification.