- EDA Products for Programmable Platforms Overview
- Programmable Synthesis Engine
- Static Timing Analysis Engine
- Routing Engine
- Automated Test and Regression Environment
Static Timing Analysis Engine
SoftJin's Static Timing Analysis Engine is an EDA building block that can be integrated to run in close loop with EDA tools involving timing optimization such as Synthesis, Placement and Routing tools. Originally designed and integrated with SoftJin's FPGA Routing Engine, SoftJin's STA engine is available as an object library with well defined interfaces for integration with other EDA tools.SoftJin's Static Timing Analysis Engine
The STA Engine has the following key features:
- The STA Engine has the capability to carry out timing analysis on the input netlist using cell delays available through .LIB and net delays available through SDF or through appropriate annotation API. The Engine computes slack values for all nets in the design and returns those through API calls.
- The STA Engine can carry out the timing analysis for both setup (max-analysis) and hold (min-analysis) violations.
- The STA Engine finds out k most critical paths and also reports maximum frequency.
- Supports sub-set of SDC constraints including false path, multi-cycle path specification.
- Support for incremental timing analysis due to Netlist change or change in net delay.
- Handles circuits with multiple clocks.
- Well Defined Interfaces to easily integrate into the design flow - The STA Engine accepts the delay information, delay constraints, cell characteristics and the design net-list in standard formats. Similarly, the STA Engine generates delay information in SDF format along with the Timing Report.
- The STA Engine interfaces with SoftJin's Routing Engine through a well defined C++ API interface. Similarly, the STA Engine can be integrated with any other third party Routing, Placement or Synthesis Engine.