• Overview
• System Design Automation
• Logic Design Automation
• Physical Design Automation
• Post Layout Tools
• GUI Development Service
• Tool QA / Validation Service
• OpenAccess Based Tool Development
• Design Flow and Methodolgy Development

Logic Design Automation

At the RTL and Logic level, SoftJin has deep expertise in Hardware Description Languages (HDLs) and HDL based tools. We have developed HDL Front Ends which parse HDLs into language independent database that can then be employed in Synthesis, Verification and other applications. In this area, SoftJin also licenses a Verilog Front End as a re-usable EDA component to enable quick development of Front End applications. SoftJin has expertise in development of HDL synthesis tools targeted at standard cells as well as FPGAs. SoftJin's Programmable Synthesis Engine (PSE) can be customized for developing optimized Synthesis tools for variety of Programmable platforms. We can also develop RTL/Logic verification tools such as Simulators and Timing Analyzers.

Some of our past projects in this domain include:

• RTL Rule CheckerSoftJin developed a RTL style checker to check for errors and unsupported constructs in the incoming RTL of a design flow of a programmable fabric



• HDL Front EndWe developed an integrated Verilog and VHDL Front End for the internal use of a large Japanese semiconductor company.
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• Enabling RTL-to-Gate Equivalence CheckingFujitsu Labs of America [FLA] accelerated its product development plans by outsourcing development of a key component of its Equivalence Checking product to SoftJin.
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