JPEG Decoder

SoftJin’s JPEG decoder IP is capable of decompressing JPEG image of any resolution. The IP capable of supporting decompression in real time applications in both SD and HD resolution image.

SoftJin’s JPEG decoder IP has been silicon proven on FPGA (Xilinx, Altera) platforms.

Key Features

Supports baseline ISO/IEC 10918-1 standard
Uses 8x8 two dimensional fixed point inverse DCT
Configurable Quantization table
Takes JPEG image as input
Supports color components in 4:4:4, 4:2:2 and 4:2:0 formats as well as black white image
The JPEG Decoder running at 100 MHz, can decompress
- 75 SD frames (720x576) of 4:4:4 formats per sec
- 15 HD frames (1920x1080) of 4:4:4 formats per sec
- 150 SD frames (720x576) of 4:2:0 formats per sec
- 30 HD frames (1920x1080) of 4:2:0 formats per sec
In a typical application it consumes 4234 LUTs and 2572 FF in Virtex5 device and tested to run at 136 MHz clock frequency

Figure below illustrates the internal architecture of the IP.

Sample Application Areas

Surveillance camera
Traffic monitoring system
High resolution still camera and camcorder
Office automation equipment like printers, scanners, digital copiers etc
Medical imaging systems
Video conference and display-projection systems

License Models and Deliverables

The IP can be licensed in source code as well as Netlist format.
In source code format the deliverables are

Verilog code
Bit and cycle accurate C model
Test Benches
Data sheet and Integration document

In Netlist format the deliverables are

Netlist compatible with Xilinx, Altera or other FPGA devices
Test Benches
Data sheet and Integration document

The IP can be licensed under a single usage license model as well as multi-usage license.

For more information about JPEG decoder please click here to download the PDF.

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To evaluate the IP please write to us at sales@softjin.com