FPGA Placement Engine
SoftJin’s FPGA Placement and Packing Engine performs Placement and packing for FPGA Architectures while optimizing for Resource Usage, Routability and Timing. It is a core EDA component that can be easily customized and tuned to develop a best-in-class Placement and Packing Tool for a specific FPGA architecture. FPGA Placement Engine adheres to FPGA Architecture specific rules to generate Legal Placement. It also supports a variety of User placement constraints related to BLE Packing, CLB Packing, Region and Location Constraints.SoftJin's FPGA Placement Engine
The FPGA Placement Engine has the following key features:
- Placement Engine optimizes for Resource usage, Routability and Timing
- Interfaces with SoftJin’s Static Timing Analysis Engine
- Uses timing information to optimize placement on timing critical paths
- Well Defined Interfaces to easily integrate into the design flow
- Reads the FPGA Architecture, Timing Constraints, User Placement constraints and Synthesized Netlist information using well-defined Interfaces
- Adheres to FPGA Architecture specific rules to generate Legal Placement
- Automatic IO placement adhering to IO placement rules
- RAM / Carry-chain placement adhering to placement rules
- Supports a variety of User placement constraints related to Logic Cell Packing, CLB Packing, Region and Location Constraints
- Supported on both Linux and Windows platform