- Overview
- System Design and Validation
- Application/ IP Development and Customization
- SoftJin's IP Portfolio
- Embedded System Design
IP and Application Development and Customization Service
SoftJin puts a lot of stress in the quality of the IPs and provide a rich portfolio of deliverables to its IP customer. Typical SoftJin's deliverable to an IP customers include, but not limited to:
- IP in C/C++, RTL (Verilog/ VHDL/ SystemC) Code
- Test-benches including synthesizable test benches
- Design Constraints File (e.g. SDC), simulation and synthesis scripts
- Datasheet/ user documentation
- Verification plan, results, functional/ code coverage reports
- Emulation of FPGA platform
SoftJin's IP Development Methodology

Customization of the IP according to the architecture of a particular platform is the key enabler to increase the IP performance on that particular platform. Especially performance of the computational intensive IPs can be increased dramatically by customization. SoftJin offers customization of IPs on different programmable platforms like FPGA, multi-core processors etc.
The flow of IP customization service is represented in the illustration on the right.
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SoftJin also help customer to verify/ qualify IPs procured from third party vendor. The services includes
IP Qualification
- IP documentation
- IP Integration and ease of re-use assessment
- Design and Verification Quality
- Analysis of Verification results
IP Verification
Develop Test benches to verify the functional correctness of the IP. These are in addition to test benches provided by IP Vendor.
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Simulation Evaluation
Behavioral Model: The behavioral (non-synthesizable) model enable IP integrator can plug-in the behavioral model into his/her design.
Pre-Compilation Simulation Library: RTL code of the IP can be provided in form of pre-compiled simulation libraries (e.g. ModelSim) in binary format.
Synthesis Evaluation
To protect the IPs SoftJin can offer the following services
- Mangling of the RTL code
- Encryption of RTL code
SoftJin's Prior Experience in Application and IP Design Service
DSP Functions: FFT/ IFFT, FIR, IIR, DCT/ IDCT
I/O Interface: USB cntl., I2C cntl., LCD cntl.
Memory Cntl.: SSRAM cntl., SDRAM cntl., EEPROM cntl.
Communication IPs: Bloom Filter, Checksum Calculator, Hamming Code recv/ transmitter, Cryptographic hash func.
Communication Application: Ingress Packet Processing for specific telecom protocol (combined header parser, scheduler, queue manager, packet editor)
Image Processing Application: Edge-detection, histograms, image scaling, image arithmetic
To know more about SoftJin's IP roadmap please send an email to sales@softjin.com
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IP Qualification
- IP documentation
- IP Integration and ease of re-use assessment
- Design and Verification Quality
- Analysis of Verification results
IP Verification
Develop Test benches to verify the functional correctness of the IP. These are in addition to test benches provided by IP Vendor.Pre-Compilation Simulation Library: RTL code of the IP can be provided in form of pre-compiled simulation libraries (e.g. ModelSim) in binary format.
SoftJin's Prior Experience in Application and IP Design Service
DSP Functions: FFT/ IFFT, FIR, IIR, DCT/ IDCTI/O Interface: USB cntl., I2C cntl., LCD cntl.
Memory Cntl.: SSRAM cntl., SDRAM cntl., EEPROM cntl.
Communication IPs: Bloom Filter, Checksum Calculator, Hamming Code recv/ transmitter, Cryptographic hash func.
Communication Application: Ingress Packet Processing for specific telecom protocol (combined header parser, scheduler, queue manager, packet editor)
Image Processing Application: Edge-detection, histograms, image scaling, image arithmetic
