EDA Tool Development Services for 3D IC Design3D Integrated circuit design is an emerging technology that addresses the demand for increased density, higher bandwidth, and low power Integrated Circuits. 3D Integrated Circuits manufactured with Through Silicon Viaís (TSV) technology enable the designers to pack more transistors in a single chip with smaller form factor. Although TSV based 3D seems to be a promising technology, it is still in early stages and demands lot of support from EDA tools. Development of new tools for 3D aware design could be extremely expensive and it would be beneficial for the designers and EDA tool vendors to make use of the existing 2D tools to the extent possible to reduce the total cost of the EDA tools. SoftJin offers customized EDA tool development and physical design methodology services for 3D IC design. SoftJinís approach involves development of new 3D specific EDA tools along with re-use of existing 2D EDA tools. SoftJin has prior experience of developing such customized 3D aware Physical Design Tools for leading semiconductor research companies.
Shown below is a representative 3D Physical Design flow, where the EDA tools are developed by considering the 3D aware design. The 3D aware tools create the basic infrastructure for 3D design and make use of the existing 2D EDA tools to create a complete design flow thus reducing the cost of the EDA tools that can be used by designers.
3D IC Physical Design Flow
- 3D Chip Planning 3D Chip planning tool includes 3D design partitioner and TSV placer. 3D Design partitioner partitions the design in multiple layers so that the P&R tools can work on each layer data as with a 2D tool. The partitioner makes use of the die area effectively by distributing the macros and standard cells for better performance. The partitioner creates the TSVís in the netlist for interconnections between the consecutive Tierís (Layers of a 3D chip). TSV Placer places the TSVís in each layer and works with the partition engine to create the optimal placement of the TSVís. TSV Placer creates optimal global placement of TSVís for all cells. In addition to the global placement, TSV placer creates detail placement of TSVís for the hard macros of the design. Both partitioner and TSV placer consider the Timing and Thermal issues while creating the 3D design.
- Tier Time Budgeting Tier Time Budgeting is an intelligent tool that analyzes the timing paths across various layers of a 3D IC. The information about the timing paths that are broken across the layers is specified as timing spec for the 2D STA tool. Using the timing spec information, 2D STA tool estimates the timing accurately for a 3D design.
- 3D Clock Tree Synthesis Plug-in 3D Clock Tree Synthesis Plugin tool is integrated along with the 2D routing tool to manage the 3D Clock distribution while creating the routes in each layer of the IC. The 3D CTS tool considers the clock skew between the layers of the 3D chip while creating the 3D aware Clock tree.
- 3D Parasitic Merge Using the flow mentioned above, the timing and power are calculated for each layer of the chip. Parasitics Merge Tool considers the timing and power information for each layer along with the parasitic affect due to the nets that are routed across layers. By combining the information about Parsitics in a 3D IC, the results are sent to the sign off tool.