Service Offerings and Core Skills

With the ASIC like density and complexity of today’s leading edge FPGA devices, the FPGA Design domain has undergone several changes. Rather than serving as mere glue logic, today’s platform FPGAs allow for complex system design. Increasingly higher speed applications are becoming feasible on FPGAs. All this is leading to larger FPGA design sizes and increasingly larger design teams to tackle the mounting design and verification challenge.

SoftJin offers FPGA Design and Verification to help you meet the above challenges that are associated with modern FPGA Design.

Offerings
SoftJin offers the following services in the area of FPGA design:

•FPGA Based System Design
•FPGA Based IP Design
•Design Verification Services
• ASIC/SoC Prototyping

Key skills

System Level Design Skills
• Algorithm development for high performance applications
• Hardware software partitioning
• Multi-FPGA partitioning
• System level architecture optimizations
• Multi-clock domain logic

FPGA Design Implementation Skills
• RTL modelling in Verilog, VHDL
• Use of Platform FPGAs
• Use of standard design elements (Embedded Processors, Memories, Bus Controllers)
• Use of industry standard tools for Synthesis and Simulation
• Physical design
• Timing closure

Design Verification Skills
• Reusable SystemC Testbenches at various abstraction levels (Transaction Level, Cycle Acuurate, RTL)
• Synthesizable Test benches for ultra fast verification
• Hardware-Software co-verification
• SystemVerilog Assertion based Verification

SoftJin's Differentiators

• Design and Realization of Algorithms for high-performance applications. As Applications increasingly become a combination of software and hardware, our high end software and algorithm development capabilities enable high performance
• Variety of Proprietary system level verification strategies to meet the verification challenge
• Expertise in Processor (MicroBlaze/NiosII) based Platform FPGA Design
• As design re-use becomes imperative, we have strong expertise in use of standard components

Verification Methodology

SoftJin offers these services based on a proprietary FPGA design and verification methodology and using the best of breed FPGA design and verification tools. SoftJin deploys SystemC to develop the test benches for the verification of the FPGA designs at the unit level and at the system level. The advantages of a SystemC based approach over conventional approach are in the areas of Integration, Modeling and Verification.

Modeling Advantage
• Allows Transaction-level, Cycle-accurate and pin-accurate models.
• Reduction in model development and verification time.

Verification Advantage
• Re-usable test bench.
• Provides direct interfaces with HDL Model.
• Provides Verification Library – SCV.

Integration Advantage
• Provides Co-verification environment.
• HDL Module can replace SystemC Module and vice-versa.
• Increases simulation speed.
• Step-by-Step module verification.